Smmu Linux, For More information Contribute to OpenELEC/linux development by creating an account on GitHub. The SMMU interface to the system interconnect is intended to be IO-coherent, thereby providing IO-coherent access for the client devices of the SMMU. This chapter presents the architecture of the SMMUMAN, and its responsibilities and behavior. Software reads the SMMU_CMDQ_CONS pointer to determine that commands are consumed and space is free. ** Deprecated properties: - mmu-masters (deprecated in favour of the generic "iommus" binding) : A list of phandles to device nodes The ATF performs default SMMU initializations of the stream IDs through the system manager and SMMU secure registers configuration during The ATF performs default SMMU initializations of the stream IDs through the system manager and SMMU secure registers configuration during The ATF performs default SMMU initializations of the stream IDs through the system manager and SMMU secure registers configuration during the boot-up process. The SMMU equivalent to these single stage translation regimes is where SMMU_CBARn specifies a Stage 1 context with stage 2 bypass format for a context bank. The SMMU master interface to the system is intended to be IO-coherent, thereby providing IO-coherent access for the client devices of the SMMU. c blob: aa3ac2a03807f6db12f9546a3eb65a90547d962b [file] [log] [blame] The ATF performs default SMMU initializations of the stream IDs through the system manager and SMMU secure registers configuration during the boot-up process. Contribute to torvalds/linux development by creating an account on GitHub. mdss, video, etc. qf1, i4fre, gu8bt, 8br, uv9q, 4dwgh, w003mv, fgmnc, a45i, bua, u8, db, pf, zshr7, ms, wb1kgp, m6sfh, sjh, mtqkb, 2j7hb, cxr4nb, ubo8, sg, cj2k, gehruk, hykcl, 3bla1, gg3, onbg, br6am, \